View ADAU1979_7582655.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

quad analog - to - digital converter (adc) data sheet ADAU1979 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or paten t rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features four 4.5 v rms (typical) differential inputs on - chip phase - locked loop ( pll ) for master clock low electromagnetic interference ( emi ) design 1 0 9 db (typical) analog - to - digital converter ( adc ) dynamic range total harmonic distortion + noise (thd + n): ? 9 5 db (typical) selectable digital high - pass filter 24- bit stereo adc with 8 khz to 192 khz sample rates digital volume control with autoramp function i 2 c/ spi controllable for flexibility software - controllable clickless mute software power - down right justified, left justified, i 2 s, and tdm modes master and slave operation modes 40- lead l fcs p package qualified for automotive applications applications automotive audio systems active noise cancellation systems general description the ADAU1979 incorporates four high performance, analog - to - digital conver ter s (adc s ) with 4.5 v rms capable ac - coupled input s . the adc s use a multibit sigma - delta ( - ) architecture with continuous time front end for low emi . an i 2 c/ serial peripheral interface (spi ) control port is included that allow s a microcontroller to adjust volume and many other parameters. the ADAU1979 uses only a single 3 .3 v supply . the device internally generates the requ ired digital dvdd supply . the low power architecture reduces the power consumption. the o n - chip pll can derive the master clock from an external c lock input or frame clock (sample rate clock). when fed with the frame clock , it eliminates the need for a separate high frequency master clock in the system . the ADAU1979 is available in a 40 - lead lfcsp package. note that throughout this data sheet, multifunction pins, such as scl/cclk, are referred to either by the entire pin name or by a single function of the pin, for example, cclk, when only that function is relevant. functional block dia gram figure 1 . avddx bg ref programmable gain decimator/hpf dc calibration serial audio port vref mclkin pll_filt avdd1 avdd3 avdd2 dgnd agnd3 agnd2 agnd1 agnd6 agnd5 agnd4 sa_mode pll agndx dvdd iovdd lrclk bclk sdataout1 sdataout2 3.3v to 1.8v regulator ADAU1979 scl/cclk sda/cout addr1/cin addr0/clatch pd/rst i 2 c/spi control agndx agndx ain1 ain1 ain2 ain2 ain3 ain3 ain4 ain4 adc adc adc adc avddx 11408-001
ADAU1979 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 analog performance specifications ........................................... 3 digital input/output specifications ........................................... 3 power supply specifications ........................................................ 4 digital filter specifications ......................................................... 4 timing specifications .................................................................. 5 abs olute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical p erformance characteristics ........................................... 10 theory of operation ...................................................................... 12 overview ...................................................................................... 12 power supply and voltage reference ....................................... 12 power - on reset sequence ........................................................ 12 p ll and clock ............................................................................. 13 analog inputs .............................................................................. 14 adc ............................................................................................. 16 adc summing modes .............................................................. 16 serial audio data output ports, dat a format ....................... 17 control ports ................................................................................... 21 i 2 c mode ...................................................................................... 21 spi mode ..................................................................................... 24 register summary .......................................................................... 26 register details ............................................................................... 27 master power and soft reset register ..................................... 27 pll control register ................................................................. 28 block power control and serial port control register ......... 29 s erial port control register 1 ................................................... 30 serial port control register 2 ................................................... 31 channel 1 and channel 2 mapping for output serial ports register ........................................................................................ 32 channel 3 and channel 4 mapping for output serial ports register ........................................................................................ 34 serial output drive control and overtemperature protection st atus register ............................................................................. 35 post adc gain channel 1 control register .......................... 36 post adc gain channel 2 control register .......................... 37 post adc gain channel 3 control register .......................... 37 post adc gain channel 4 control register .......................... 38 high - pass filter and dc offset control register and master mute register .............................................................................. 38 adc clipping status register .................................................. 39 digital dc high - pass filter and calibration register .......... 40 typical application circuit ........................................................... 41 outline dimensions ....................................................................... 42 ordering guide .......................................................................... 42 automotive products ................................................................. 42 revisio n history 11 /13 revision 0: initial version rev. 0 | page 2 of 44
data sheet ADAU1979 rev. 0 | page 3 of 44 specifications performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specif ications. avddx/iovdd = 3.3 v; dvdd (internally generated) = 1.8 v; t a = ? 40 c to +105c, unless otherwise noted . m aster clock = 12 .288 mhz (48 khz f s , 256 f s mode); input sample rate = 48 khz; measurement bandwidth = 20 hz to 20 khz; word width = 24 bits; load capacitance (digital output) = 20 pf; load current (digital output) = 1 ma; digital input voltage high = 2.0 v; and digital input voltage low = 0.8 v. analog performance s pecifications table 1. parameter test conditions /comments min typ max unit line input full scale ac differential input voltage 4.18 4.5 4.82 v rms full scale single -e nded input voltage 2.09 2.25 2.41 v rms input common - mode voltage v in, cm at ainx/ ainx pins 1.5 v dc analog - to - digital converters differential input resistance between ainx and ainx 64.34 k single - ended input resistance between ainx and ainx 32.17 k adc resolution 24 bits dynamic range (a - weighted) line input 1 input = 1 khz, ?60 dbfs (0 dbfs = 4.5 v rms input) 103 109 db total harmonic distortion + noise ( thd + n ) input = 1 khz, ? 1 dbfs ( 0 dbfs = 4.5 v rms i nput) ? 9 5 ? 8 7 db digital gain post adc 0 60 db gain error ? 10 +10 % interchannel gain mismatch ? 0.25 +0. 25 db gain drift 100 ppm/c common - mode rejection ratio ( cmrr ) 400 m v rms, 1 khz 50 65 db 400 m v rms, 20 khz 56 db power supply rejection ratio ( psrr ) 100 mv rms, 1 khz on avdd = 3.3 v 70 db interchannel isolation 100 db interchannel phase deviation 0 degrees reference internal reference voltage vref pin 1.47 1.50 1.54 v output impedance 20 k adc serial port output sample rate 8 192 khz 1 this is for a sampling frequency, f s , ranging from 44.1 khz to 192 khz. digital input/output specifications table 2. parameter test conditions/comments min typ max unit input high level input voltage (v ih ) 0.7 iovdd v low level input voltage (v il ) 0.3 iovdd v input leakage current ? 10 + 10 a input capacitance 5 pf output high level output voltage (v oh ) i oh = 1 ma iovdd ? 0.60 v low level output voltage (v ol ) i ol = 1 ma 0.4 v
ADAU1979 data sheet rev. 0 | page 4 of 44 power supply specifi cations avdd = 3.3 v, dvdd = 1.8 v, iovdd = 3.3 v, and f s = 48 khz (master mode), unless otherwise noted . table 3. parameter test conditions/comments min typ max unit supply dvdd o n - chip low dropout ( ldo ) regulator 1.62 1.8 1.98 v avddx 3.0 3.3 3.6 v iovdd 1.62 3.3 3.6 v iovdd current m aster clock = 256 f s normal operation f s = 48 khz 450 a f s = 96 khz 880 a f s = 192 khz 1.75 m a power - down f s = 48 khz to 192 khz 20 a a vdd x current normal operation 4 - channel adc , dvdd i nternal 14 ma 4- channel adc, dvdd e xternal 9.5 ma power - down 270 a dvdd current normal operation dvdd e xternal 5 ma power - down 65 a power dissipation normal operation master clock = 256 f s , 48 khz analog supply dvdd i nternal 46.2 mw dvdd e xternal 31 mw digital supply dvdd e xternal 8.1 mw digital i/o supply iovdd = 3.3 v 1. 49 mw power - down, all supplies 960 w digital filter specifications table 4. parameter mode factor min typ max unit adc decimation filter all modes, typical at f s = 48 khz pass band 0.4375 f s 21 khz pass - band ripple 0.015 db transition band 0.5 f s 24 khz stop band 0.5625 f s 27 khz stop - band attenuation 79 db group delay f s = 8 khz to 96 khz 22.9844/ f s 479 s f s = 192 khz 35 s high - pass filter all modes, typical at 48 khz cutoff frequency at ?3 db point 0.9375 hz phase deviation at 20 hz 10 degrees settling time 1 sec adc digital gain all modes 0 60 db gain step size 0.375 db
data sheet ADAU1979 rev. 0 | page 5 of 44 timing specification s table 5. limit at parameter t min t max unit description input master clock (mclk) duty cycle 40 60 % mclkin duty cycle; mclkin at 256 f s , 384 f s , 512 f s , and 768 f s f mclkin see table 9 mhz mclkin frequency, pll in mclk mode reset reset pulse , t reset 15 ns rst low pll lock time 10 ms adc serial output port see figure 2 t abh 10 ns bclk high, slave mode t abl 10 ns bclk low, slave mode t als 10 ns lrclk setup to bclk rising, slave mode t alh 5 ns lrclk hold from bclk rising, slave mode t abdd 18 ns sdataoutx delay from bclk falling spi port see figure 3 f cclk 10 mhz cclk frequency t ccph 35 ns cclk high t ccpl 35 ns cclk low t cds 10 ns cin setup to cclk rising t cdh 10 ns cin hold from cclk rising t cls 10 ns clatch setup to cclk rising t clh 40 ns clatch hold from cclk rising t clph 10 ns clatch high t coe 30 ns cout enable from clatch falling t cod 30 ns cout delay from cclk falling t cots 30 ns cout tristate from clatch rising i 2 c port see figure 4 f scl 400 khz scl frequency t sclh 0.6 s scl high t scll 1.3 s scl low t scs 0.6 s setup time; relevant for repeated start condition t sch 0.6 s hold time; after this period of time, the first clock pulse is generated t ds 100 ns data setup time t dh 0 data hold time t scr 300 ns scl rise time t scf 300 ns scl fall time t sdr 300 ns sda rise time t sdf 300 ns sda fall time t bft 1.3 s bus - free time; time between stop and start t susto 0.6 s setup time for stop condition
ADAU1979 data sheet rev. 0 | page 6 of 44 timing di a grams figure 2 . adc serial output port timing figure 3 . spi port timing figure 4 . i 2 c port timing bclk lrclk sdataoutx left justified mode sdataoutx right justified mode lsb sdataoutx i 2 s mode msb msb ? 1 msb msb 8-bit clocks (24-bit data) 12-bit clocks (20-bit data) 14-bit clocks (18-bit data) 16-bit clocks (16-bit data) t abl t als t abdd t abdd t abh t abdd t alh 1 1408-002 clatch cclk cin cout t cls t cds t cdh t cod t ccph t ccpl t clh t clph t coe t cots 1 1408-003 t sch t sclh t scr t scll t scf sda scl t sch t scs t dh t sdf t sdr t ds stop start t susto t bft 1 1408-004
data sheet ADAU1979 rev. 0 | page 7 of 44 absolute maximum rat ings table 6. parameter rating analog (avdd x ) supply ? 0.3 v to +3.6 v digital supply dvdd ?0.3 v to +1.98 v iovdd ?0.3 v to +3.63 v input current (except supply pins) 20 ma analog input voltage (signal pins) ? 0.3 v to + 3.6 v digital input voltage (signal pins) ?0.3 v to +3.6 v operating temperature range ( ambient ) ?40c to +1 0 5c junction temperature range ?40c to +125c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja represents junction - to - ambient thermal resistance, and jc represents the junction - to - case thermal res istance. all characteristics are for a standard jedec board per jesd51. table 7 . thermal resistance package type ja jc unit 40- lead l fcsp 32.8 1.93 c/w esd caution
ADAU1979 data sheet rev. 0 | page 8 of 44 pin configuration an d function description s figure 5 . pin configuration table 8. pin function descriptions pin no. mnemonic type 1 description 1 agnd1 p analog ground. 2 vref o voltage reference. decouple vref to agnd with a 10 f capacitor in parallel with a 100 nf capacitor . 3 pll_filt o p hase - locked loop filter . return pll_filt to avdd using recommended loop filter components. 4 avdd2 p analog power supply. connect avdd2 to an analog 3.3 v supply. 5 agnd2 p analog ground. 6 pd / rst i power - down/ reset (active low). 7 mclkin i master clock input. 8 , 23 to 27, 30 nc no connect . do not connect to the s e pin s . l eave the nc pins open. 9 sa_mode i stand a lone mode. connect sa_mode to iovdd using a 10 k pull - up resistor for s tand a lone m ode. 10 dvdd o 1.8 v digital power supply output. decouple dvdd to dgnd with 100 n f and 10 f capacitor s . 11 dgnd p digital ground. 12 iovdd p digital i / o power supply. connect iovdd to a supply from 1.8 v to 3.3 v. 13 sdataout1 o adc serial data output pair 1 (adc l1 and adc r1). 14 sdataout2 o adc serial data output pair 2 (adc l2 and adc r2). 15 lrclk i/o frame clock for adc serial port. 16 bclk i/o bit clock for adc s erial port. 17 sda/cout i/o serial data input/ out put ( i 2 c ) /control data output (spi). 18 scl/cclk i serial clock input ( i 2 c ) /control clock input (spi). 19 addr0/ clatch i chip address b it 0 setting ( i 2 c) /chip select input for control data (spi). 20 addr1/cin i chip address b it 1 setting ( i 2 c) /control data input (spi). 21 agnd3 p analog ground. 22 agnd4 p analog ground. 28 agnd5 p analog ground. 29 agnd6 p analog ground. 1 agnd1 2 vref 3 pll_filt 4 avdd2 5 agnd2 7 mclkin 8 nc 9 sa_mode 10 dvdd 23 nc 24 nc 25 nc 26 nc 27 nc 28 agnd5 29 agnd6 30 nc 22 agnd4 21 agnd3 11 dgnd 12 iovdd 13 sdataout1 15 lrclk 17 sda/cout 16 bclk 18 scl/cclk 20 addr1/cin 14 sdataout2 33 ain1 34 ain2 35 ain2 36 ain3 37 ain3 38 ain4 39 ain4 40 avdd1 32 ain1 31 avdd3 top view (not to scale) ADAU1979 6 pd/rst 19 addr0/clatch notes 1. nc = no connect. do not connect to these pins. leave the nc pins open. 2. the exposed pad must be connected to the ground plane on the printed circuit board (pcb). 1 1408-005
data sheet ADAU1979 rev. 0 | page 9 of 44 pin no. mnemonic type 1 description 31 avdd3 p analog power supply. connect avdd3 to an analog 3.3 v supply. 32 ain1 i analog input channel 1 inverting i nput . 33 ain1 i analog input channel 1 noninverting input. 34 ain2 i analog input channel 2 inverting input. 35 ain2 i analog input channel 2 noninverting input. 36 ain3 i analog input channel 3 inverting input. 37 ain3 i analog input channel 3 noninverting input. 38 ain4 i analog input channel 4 inverting input. 39 ain4 i analog input channel 4 noninverting input. 40 avdd1 p analog power supply. connect avdd1 to an analog 3.3 v supply. ep exposed pad. the exposed pad must be connected to the ground plane on the printed circuit board (pcb). 1 p = power, o = output, i = input, i/o = input/output.
ADAU1979 data sheet rev. 0 | page 10 of 44 typical performance characteristics figure 6 . fast fourier transform, 4 . 5 mv differential input at f s = 48 khz figure 7 . fast fourier transform, ?1 dbfs differential input figure 8 . thd + n vs. input amplitude figure 9 . cmrr differential input, referenced to 4 5 0 m v differential input figure 10 . fast fourier transform, no input figure 11 . adc pass - band ripple at f s = 48 khz 20 100 1k 10k 20k ?160 10 0 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 frequency (hz) amplitude (dbfs) 11408-006 20 100 1k 10k 20k ?160 10 0 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 frequency (hz) amplitude (dbfs) 11408-007 10m 5m 100m 1 5 ?120 0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 input level (v rms) thd + n (dbfs) 11408-008 ?100 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 cmrr (db) 11408-009 20 100 1k 10k 20k frequency (hz) 20 100 1k 10k 20k ?160 10 0 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 frequency (hz) amplitude (dbfs) 1 1408-010 0.10 0.08 0.06 0.04 0.02 0 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 18000 16000 14000 12000 10000 8000 6000 4000 2000 magnitude (db) frequency (hz) 1 1408-0 1 1
data sheet ADAU1979 rev. 0 | page 11 of 44 figure 12 . adc filter stop - band response at f s = 48 khz 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 40000 5000 10000 15000 20000 25000 30000 35000 magnitude (db) frequency (hz) 1 1408-012
ADAU1979 data sheet rev. 0 | page 12 of 44 theory of operation overview the ADAU1979 incorporates four high performance adcs and a phase - locke d loop (pll) circuit for generating the necessary on - chip clock signals. power supply and vol tage reference the ADAU1979 requires a single 3.3 v power supply. decouple a ll avddx pins to the nearest agnd x pin with 100 nf ceramic chip capacitors placed as near the avddx pins as possible to minimize noise pi ckup. a bulk aluminum electro lytic capacitor of at least 10 f must be provided on the same pcb as the adc. it is important that the analog supply be as clean as possible for best performance. the supply voltage for the digital core (dvdd) is generated us ing an internal low dropout regulator. the typical dvdd output is 1.8 v and must be decoupled using a 100 nf ceramic capacitor and a 10 f capacitor. place the 100 nf ceramic capacitor as near the dvdd pin as possible . the voltage reference for the analog blocks is generated internally and output at the vref pin (pin 2). the typical voltage at the vref pin is 1.5 v with an avddx of 3.3 v. all digital inputs are compatible with ttl and cmos levels. all outputs are driven from the iovdd supply. the iovdd can be in the 1.8 v to 3.3 v range . the iovdd pin must be decoupled with a 100 nf capacitor placed as near the iovdd pin as possible. the adc internal voltage reference is output from the vref pin and must be decoupled using a 100 nf ceramic capacitor in paral lel with a 10 f capacitor. the vref pin has limited current capability. the voltage reference is used as a reference to the adc; therefore, it is recommended not to draw current from this pin for external circuits. when using this reference, use a noninve rting amplifier buffer to provide a reference to other circuits in the application. in reset mode, the vref pin is disabled to save power and is enabled only when the pd / rst pin is pulled high. power - on reset sequence th e ADAU1979 requires that a single 3.3 v power supply be provided externally at the avddx pin. the device internally generates dv dd (1.8 v), which is used for the digital core of the adc. the dvdd supply output pin (pin 10) is provided to connect the decoupling capacitors to dgnd. the typical recommended values for the decoupling capacitors are 100 nf in parallel with 10 f. during a reset, the dvdd regulator is disabled to reduce power consumption. after the pd / rst pin (pin 6) is pulled high, the device enables the dvdd regulator. however, the internal adc and digital core reset are controlled by the internal power - on reset (por) signal circuit, which monitors the dvdd level. therefore, the device does not exit a reset until dvdd reaches 1.2 v and the por signal is released. the dvdd settling time depends on the charge - up time for the external capacitors and on the avddx ramp - up time. the internal por circuit is provided with hysteresis to ensure that a reset of the device is not initiated by an instantaneous glitch on dvdd. the typical trip points are 1.2 v with pd / rst high and 0.6 v (20%) with pd / rst low. this ensures that the core is not reset until the dvdd level falls below the 0.6 v trip point. as soon as the pd / rst pin is pulled high, the internal regulator starts charging up c ext on the dvdd pin. the dvdd charge - up time is based on the output resistance of the regulator and the external decoupling capacitor. the time constant can be calcu - lated as t c = r out c ext w here r out = 20 ? typical. for example, if c ext is 10 f, t c is 200 s and is the time that it takes to reach the dvdd voltage, within 63.6%. the power - on reset circuit releases an internal reset of the core when dvdd reaches 1.2 v (see figure 13 ). therefore, it is recommended to wait for at least the t c period to elapse bef ore sending i 2 c or spi control signals. figure 13 . power - on reset timing when applying a hardware reset to the device by pulling the pd / rst pin (pin 6) low and then high, there are certain time restrictions. during the pd / rst low pulse period, the dvdd starts discharging. the discharge time constant is determined by the internal resistance of the regulator and c ext . use the following equation to estimate t he time required for dvdd to fall fro m 1.8 v to 0.48 v (0.6 v ? 20%) : t d = 1.32 r int c ext where r int = 64 k? typical. ( r int can vary due to process by 20%.) for example, if c ext is 10 f, t d is 0.845 sec. depending on c ext , t d may vary and , in turn , affect the mini - mum hold period for the pd / rst pulse. the pd / rst pulse must be held low for the entire t d time period to ini tialize the core properly. 1.2v 0.48v por dvdd (1.8v) pd/rst avddx t reset t d t c 1 1408-013
data sheet ADAU1979 rev. 0 | page 13 of 44 reduce t he required pd / rst low pulse period by adding a resistor across c ext . calculate t he new t d value c as t d = 1.32 r eq c ext where r eq = 64 k? || r ext . the resistor ensures that dvdd not only discharges quickly during a reset or an avddx power loss but also resets the internal blocks correctly. note that some power loss in this resistor is to be expected because the resistor constantly draws current from dvdd. the typical value for c ext is 10 f and 3 k? for r ext . this results in a time constant of t d = 1.32 r eq c ext = 37.8 ms where r eq = 2.866 k? (64 k? || 3 k?). using this equation at a set c ext value, the r ext can be calculated for a desired pd / rst pulse period. there is also a software reset bit (s_rst, bit 7 of register 0x00) available that can be used to reset the part, but note that during an avddx power loss, the software reset may not ensure proper initial ization because dvdd may not be stable. figure 14 . dvdd regulator output connections pll and cloc the ADAU1979 has a built - in analog pll to provide a jitter - free master clock to the internal adc. the pll must be programmed for the a ppropriate input clock frequency. the pll _c ontrol register 0x01 sets the pll. the clk_s bit (bit 4) of register 0x01 set s the clock source for the pll. the clock source can be either the mclkin pin or the lrclk pin (slave mode). in lrclk mode, the pll sup port s sample rates between 32 khz and 192 khz. in mclk input mode, the mcs bits (bits[2:0] of register 0x01) must be set to the desired input clock frequency for the mclkin pin. table 9 shows the master clock input frequency required for the most common sample rates and the mcs bit settings. the pll_lock bit (bit 7) of register 0x01 indicates the lock status of the pll. it is recommended that the pll lock status be rea d after initial power - up to ensure that the pll outputs the correct frequency before unmuting the audio outputs. table 9 . required master clock input frequency for common sample rates mcs (bits[2:0]) f s (khz) frequency multiplication ratio mclkin frequency (mhz) 000 32 128 f s 4.096 001 32 256 f s 8.192 010 32 384 f s 12.288 011 32 512 f s 16.384 100 32 768 f s 24.576 000 44.1 128 f s 5.6448 001 44.1 256 f s 11.2896 010 44.1 384 f s 16.9344 011 44.1 512 f s 22.5792 100 44.1 768 f s 33.8688 000 48 128 f s 6.144 001 48 256 f s 12.288 010 48 384 f s 18.432 011 48 512 f s 24.576 100 48 768 f s 36.864 000 96 64 f s 6.144 001 96 128 f s 12.288 010 96 192 f s 18.432 011 96 256 f s 24.576 100 96 384 f s 36.864 000 192 32 f s 6.144 001 192 64 f s 12.288 010 192 96 f s 18.432 011 192 128 f s 24.576 100 192 192 f s 36.864 the pll can accept the audio frame clock (sample rate clock) as the input, but the serial port must be configured as a slave , and the frame clock must be fed to the device from the master. it is strongly recommended that the pll be disabled, reprogrammed with the new setting, and then reenabled. a lock bit is provided that is polled via i 2 c to check whether the pll has acquired lock. the pll requires an external filter, which is connected at the pll_filt pin (pin 3). the recommended pll filter circuit for mclk or lrclk mode is shown in figure 15 . using npo capacitors is recommended for temperature stability. place the filter components near the device for best performance. figure 15 . pll filter 3.3v to 1.8v regulator dvdd ADAU1979 iovdd +1.8v or +3.3v c 0.1f c 0.1f c ext 10f mlcc x7r r ext 3k? avdd1 avdd3 avdd2 +3.3v to internal blocks 11408-114 avddx pll_filt lrclk mode 39nf 4.87k? 2.2nf avddx pll_filt mclk mode 5.6nf 1k? 390pf 1 1408-014
ADAU1979 data sheet rev. 0 | page 14 of 44 analog inputs the ADAU1979 has four differential analog inputs. the adcs can accommodate both dc - and ac - coupled input signals. the bl ock diagram shown in figure 16 represents the typical input circuit. in most audio applications, the dc content of the signal is removed by using a coupling capacitor . however, the adau197 9 consists of a unique input structure that allows ac coupling of the input signal s. the typical input resistance is approximately 32 k? from each input to agnd x . the hi gh - pass filter has a 1.4 hz, 6 db per octave cutoff at a 48 khz sample rate. the cutoff frequency scales directly with the sample frequency. however, care is required in dc - coupled applications to ensure that the common - mode dc voltage does not exceed the specified limit. the input required for the full - scale adc output (0 dbfs) is typically 4.5 v rms differential. figure 16 . analog input block v ref ainxp ainxn v id = v input differential v cm at ainxp/ainxn = 1.5v 32.17k 14.3k 14.3k 32.17k 1 1408-015
data sheet ADAU1979 rev. 0 | page 15 of 44 line inputs this section describes some of the possible methods to connect the line level inputs of the ADAU1979 . line input balanced or differential input dc - coupled case f or an input signal of 4.5 v rms differential with a pproximately 1.5 v common - mode dc, t he signal at each input pin has a 2 .2 5 v rms or 6. 36 v p - p signal swing. at a common - mode dc of 1.5 v, the signal can swing between (1.5 + 3.18 ) = 4. 68 v and (1.5 C 3.1 8 ) = ? 1. 6 8 v at each input . therefore, this is approximately 1 2 .72 v p - p differential across ainx and ainx and measures near 0 dbfs ( ac only with a dc high - pass filter) at the adc output (s ee figure 17 ) . line input balanced or differential input ac - coupled case for connecting the adau197 9 to a head unit amplifier output , ac coupling is recommended. in this case , the ainx/ ainx pins are at a common - mode level of 1.5 v. use the attenuator to reduce the inp ut level if it i s more than 4.5 v rms. use the following equation to identify t he c1 and c2 values for the required low frequency cutoff : c1 or c2 = 1/(2 f c input resistance ) where the input resistance of the ADAU1979 is 32 .17 k ? typ ical . refer to figu re 18 for information about connecting the line level inputs to the ADAU1979 . line input unbalanced or single - ended , pseudo differential ac - coupled case for a single - ended application , reduce th e signal swing by half because only one input is used for the signal and the other is connected to 0 v. doing t his reduces the input signal capability to 2 .2 5 v rms in the single - ended application and measure s a pproxi mately ? 6.16 dbfs ( a c only with a dc high - pass filter) at the adc output. see figure 19 for additional information. the value of c1/c2 is similar to the balanced ac - coupled case previously mentioned in the line input balanced or differential input ac - coupled case section . figure 17 . connecting the line level inputs differential dc - coupled case figure 18 . connecting the line level inputs differential ac - coupled case figure 19 . connecting the line level inputs pseudo differential ac - coupled case ainx ainx v diff = 4.5v rms ac v cm = 1.5v dc typical audio power amplifier output option a: differential dc-coupled 1 1408-016 ainx c1 c2 ainx typical audio power amplifier output option b: differential ac-coupled attenuator v diff = 2v rms 1 1408-017 ainx c1 c2 ainx v in = 2v rms ac typical audio power amplifier output option c: pseudo differential ac-coupled 1 1408-018
ADAU1979 data sheet rev. 0 | page 16 of 44 adc the ADAU1979 contains four - adc channels configured as two stereo pairs with configurable differential/single - ended inputs. the adc can operate at a nominal sample rate of 32 khz up to 192 khz. the adcs include on - board digital antialiasing filters with 79 db stop - band attenuation an d linear phase response. digital outputs are supplied through two serial data output pins (one for each stereo pair) and a common frame clock (lrclk) and bit clock (bclk). alternatively, one of the tdm modes can be used to support up to 16 channels on a si ngle tdm data line. with smaller amplitude input signals, a 10 - bit programmable digital gain compensation for an individual channel is provided to scale up the output word to full scale. take care to avoid overcompensation (large gain compensation), which leads to clipping and thd degradation in the adc. the adcs also have a dc offset calibration algorithm to null the systematic dc offset of the adc. this feature is useful for dc measurement applications. adc summing modes the four adcs can be grouped into either a single stereo adc or a single mono adc to increase the snr for the application. two options are available: one option for summing two channels of the adc and another option for summing all four channels of the adc . summing is performed in the digital block. 2 - channel summing mode when the sum_mode b its (bits[7:6] of register 0x0e) are set to 01, the channel 1 and channel 2 adc data are combined and output from the sdataout1 pin. similarly, the channel 3 and channel 4 adc data are combined and output from the sdataout2 pin. as a result, the snr improves by 3 db. for this mode, both channel 1 and channel 2 must be connected to the same input signal source. similarly, channel 3 and channel 4 must be connect ed to the same input signal source. figure 20 . 2 - channel summing mode connection diagram 1 - channel summing mode when the sum_mode bits (bits[7:6] of register 0x0e) are set to 10, the channel 1 through channel 4 adc data are combi ned and output from the sdataout1 pin. as a result, the snr improves by 6 db. for this mode, all four channels must be connected to the same input signal source. figure 21 . 1 - channel summing mode connection diagram option b: differential ac-coupled c1 v diff = 4.5v rms c2 ain1 ain1 ain2 ain2 typical stereo output c3 c4 ain3 ain3 ain4 ain4 1 1408-019 option b: differential ac-coupled c1 v diff = 4.5v rms c2 ain1 ain1 ain2 ain2 typical stereo output ain3 ain3 ain4 ain4 11408-020
data sheet ADAU1979 rev. 0 | page 17 of 44 seria l audio data output ports , data format the serial audio port comprises four pins: bclk, lrclk, sdataout1, and sdataout2. the ADAU1979 adc outputs are available on the sdataout1 and sdataout2 pins in serial format. the bclk and lrclk pins serve as the bit clock and frame clock, respectively. the port can be operated as a master or slave and can be set either in stereo mode (2 - channel mode) or in tdm multichannel mode. the supported popular audio formats are i 2 s, left justified (lj), and right justified (rj). stereo mode in 2 - channel or stereo mode, the sdataout1 output s adc data for channel 1 and channel 2, and the sdatout2 outputs adc data for channel 3 and channel 4. figure 22 through figure 24 show the supported audio formats. figure 22 . i 2 s audio format figure 23 . l eft j ustified audio format figure 24 . r ight j ustified audio format bclk lrclk sdataout1 (i 2 s mode) sdataout2 (i 2 s mode) notes 1. sai = 0. 2. sdata_fmt = 0 (i 2 s). channel 1 channel 2 8 to 32 bclks 8 to 32 bclks channel 3 channel 4 1 1408-024 bclk lrclk sdataout1 (lj mode) sdataout2 (lj mode) channel 1 channel 2 channel 3 channel 4 notes 1. sdata_fmt = 1 (lj). 1 1408-025 bclk lrclk sdataout1 (rj mode) sdataout2 (rj mode) channel 1 channel 2 channel 3 channel 4 notes 1. sdata_fmt = 2 (rj, 24-bit). 1 1408-026
ADAU1979 data sheet rev. 0 | page 18 of 44 tdm mode register 0x05 through register 0x08 provide programmability for the tdm mode. the tdm slot width, data width, and channel assignment, as well as the pin used to output the data, are programmable. by default, serial data is output on the sdataout1 pin; however, the sdata_sel bit (bit 7 of register 0x06) can be used to change the setting so that serial data is output from the sdataout2 pin. the tdm mode supports two , four , eight , or 16 channels. the ADAU1979 outputs four channels of data in the assigned slots ( figure 27 shows the tdm mode slot assignments). during the unused slots, the output pin becomes high - z so that th e same data line can be shared with other devices on the tdm bus. the tdm port can be operated as either a master or a slave. in master mode, the bclk and lrclk pins are output from the ADAU1979 , whereas in slave mode, the bclk and lrclk pins are set to receive the clock from the master in the system. both the nonpulse and pulse modes are supported. in nonpulse mode, the lrclk signal is typically 50% of the duty cycle, whereas in pulse mode, the lrclk signal must be at least one bclk wide (see figure 25 and figure 26). figure 25 . tdm nonpulse mode audio format figure 26 . tdm pulse mode audio format bclk lrclk sdata i 2 s sdata lj channel 1 channel 2 channel n 32/24/16 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 32/24/16 bclks 32/24/16 bclks sdata i 2 s channel 1 channel 2 channel n 24 or 16 bclks 24 or 16 bclks 24 or 16 bclks notes 1. sai = 001 (2 channels), 010 (4 channels), 011 (8 channels), 100 (16 channels). 2. sdata_fmt = 00 (i 2 s), 01 (lj), 10 (rj, 24-bit), 11 (rj, 16-bit). 3. bclk_edge = 0. 4. lr_mode = 0. 5. slot_width = 00 (32 bclks), 01 (24 bclks), 10 (16 bclks). 1 1408-027 bclk lrclk sdata i 2 s sdata lj channel 1 channel 2 channel n 32/24/16 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 32/24/16 bclks 32/24/16 bclks sdata i 2 s channel 1 channel 2 channel n 24 or 16 bclks 24 or 16 bclks 24 or 16 bclks notes 1. sai = 001 (2 channels), 010 (4 channels), 011 (8 channels), 100 (16 channels) 2. sdata_fmt = 00 (i 2 s), 01 (lj), 10 (rj, 24-bit), 11 (rj, 16-bit) 3. bclk_edge = 0 4. lr_mode = 1 5. slot_width = 00 (32 bclks), 01 (24 bclks), 10 (16 bclks) 1 1408-028
data sheet ADAU1979 rev. 0 | page 19 of 44 figure 27 . tdm mode slot assignment table 10 . bit clock frequency tdm mode bclk frequency mode 16 bit clocks per slot 24 bit clocks per slot 32 bit clocks per slot tdm2 32 f s 48 f s 64 f s tdm4 64 f s 96 f s 128 f s tdm8 128 f s 192 f s 256 f s tdm16 256 f s 384 f s 512 f s the bit clock frequency depends on the sample rate, the slot width, and the number of bit clocks per slot. use table 10 to calculate the bclk frequency. the sample rate (f s ) can range from 8 khz up to 192 khz. however, in master mode, the maxi mum bit clock frequency (bclk) is 24.576 mhz. for example, for a sample rate of 192 khz, 128 f s is the maximum possible bclk frequency. therefore, only 128 - bit clock cycles are available per tdm frame. there are two options in this case: either operate w ith a 32- bit data width in tdm4 or operate with a 16 - bit data width in tdm8. in slave mode, this limitation does not exist because the bit clock and frame clock are fed to the ADAU1979 . various combinations of bclk frequencies and mode s are available, but take care to choose the combination that is most suitable for th e application. number of bclk cycles = (number of bclks/slot) number of slots slot2 slot1 slot1 slot2 slot3 slot4 slot1 slot2 slot3 slot4 slot5 slot6 slot7 slot8 slot1 slot2 slot3 slot4 slot5 slot6 slot7 slot8 slot9 slot10 slot11 slot12 slot13 slot14 slot15 slot16 lrclk bclk sdataoutx?tdm2 sdataoutx?tdm4 sdataoutx?tdm8 sdataoutx?tdm16 data width 16/24 bits slot width 16/24/32 bits high-z high-z 11408-029
ADAU1979 data sheet rev. 0 | page 20 of 44 connection options figure 28 through figure 32 show the available options for connecting the serial audio port in i 2 s or tdm mode. in tdm mode, it is recommended to include a pull - down resistor on the data signal to prevent the line from floating when the sdataoutx pin of the ADAU1979 becomes high - z d uring an inactive period. select a resistor value such that no more than 2 ma is drawn from the sdataoutx pin. although the resistor value is typically in the 10 k? to 47 k? range , the appropriate resistor value depends on the devices on the data bus. fi gure 28 . serial port connection option 1 i 2 s/l eft j ustified /r ight j ustified mode s , ADAU1979 master figure 29 . serial port connection option 2 i 2 s/left justified/right justified mode s , ADAU1979 slave figure 30 . serial port connection option 3 tdm mode, ADAU1979 master figure 31 . serial port connection option 4 tdm mode, second adc master figure 32 . serial port connection option 5 tdm mode, dsp master dsp slave master ADAU1979 bclk lrclk sdataout1 sdataout2 1 1408-030 dsp master slave ADAU1979 bclk lrclk sdataout1 sdataout2 1 1408-033 dsp slave master ADAU1979 bclk lrclk sdataoutx slave ADAU1979 or similar adc bclk lrclk sdataoutx 1 1408-031 dsp slave slave ADAU1979 bclk lrclk sdataoutx master ADAU1979 or similar adc bclk lrclk sdataoutx 1 1408-034 dsp master slave ADAU1979 bclk lrclk sdataoutx slave ADAU1979 or similar adc bclk lrclk sdataoutx 1 1408-032
data sheet ADAU1979 rev. 0 | page 21 of 44 control ports the ADAU1979 control port allows two modes of operation , e ither 2 - wire i 2 c mode or 4 - wire spi mode , for setting the internal registers of the device . both the i 2 c and spi modes allow read and write capability of the registers. all the registers are eight bits wide. the registers start at address 0x00 and end at address 0x1a. the control port in both i 2 c and spi modes is slave only and, therefore, requires the master in the system to operate. the registers can be accessed with or without the master clock to the device . however, to operate the pll, serial audio ports, and boost converter, the master clock i s necessar y. by default, the ADAU1979 operates in i 2 c mode, but the device can be put into spi mode by pulling the clatch pin low three times . the control port pins are multifunctional, depending on the mode in which the device is operating. tabl e 12 describes the control port pin functions in both modes. i 2 c mode the ADAU1979 supports a 2 - wire serial (i 2 c - compatible) bus protocol. two pins, serial data (sda) and serial clock (scl), are used to communicate with the system i 2 c master controller. in i 2 c mode, t he ADAU1979 is always a slave on the bus, meaning that it cannot initiate a data transfer. each slave device on the i 2 c bus is recognized by a unique device address. the device address and r/ w byte for the ADAU1979 are shown in table 11 . the address resides in the first s even bits of the i 2 c write. bit 7 and bit 6 of the i 2 c address for the ADAU1979 are set by the levels on the addr1 and addr0 pins. the lsb of the first i 2 c byte (the r/ w bit) from the master identifies whether it is a read or write operation. logic level 1 in the lsb (bit 0) corresponds to a read operation, and logic level 0 corresponds to a write operation. table 11 . i 2 c first byte format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr1 addr0 1 0 0 0 1 r/ w the first seven bits of the i 2 c chip address for the ADAU1979 are xx10001. set bit 7 and bit 6 of the address byte using the addr1 and addr0 pins , which set the chip address to the desired value. the 7 - bit i 2 c device address can be set to one of four of the following possible options using the addr1 and addr0 pins: ? i 2 c device address 0010001 (0x11) ? i 2 c device address 0110001 (0x31) ? i 2 c device address 1010001 (0x51) ? i 2 c device address 1110001 (0x71) in i 2 c mode, both the sda and scl pins require t hat an appropriate pull - up resistor be connected to iovdd. ensure that the voltage on these signal lines does not exceed the voltage on the iovdd pin . figure 44 shows a typical connection diagram for the i 2 c mode. calculate t he value of the pull - up resistor for the sda or scl pin as follows. minimum r pull up = ( iovdd ? v il )/ i sink where: iovdd is the i/o supply voltage, typically ranging from 1.8 v up to 3.3 v. v il is t he maximum voltage at logic level 0 (that is, 0.4 v, as per the i 2 c specifications). i sink is the current sink capability of the i/o pin. t he sda pin can sink 2 ma of current; therefore, the minimum value of r pull up for an iovdd of 3.3 v is 1.5 k?. depending on the capacitance of the printed circuit board, the speed of the bus can be restricted to meet the rise time and fall time specifications. for fast mode with a bit rate of around 1 mbps, the rise time must be less than 550 ns. use the following equation to determine whether the rise time specification can be met: t = 0.8473 r pull up c board where c board must be less than 236 pf to meet the 300 ns rise time requirement. for the scl pin, the calculations depend on the current sink capability of the i 2 c master used in the system. table 12 . control port pin functions i 2 c mode spi mode pin no. mnemonic pin function pin type pin function pin type 17 sda/cout sda data i/o cout data o 18 scl/cclk scl clock i cclk clock i 19 addr0/ clatch i 2 c device address bit 0 i clatch chip select i 20 addr1/cin i 2 c device address bit 1 i cin data i
ADAU1979 data sheet rev. 0 | page 22 of 44 addressing initially, each device on the i 2 c bus is in an idle state and monitors the sda and scl lines for a start condition and the proper address. the i 2 c master initiates a data transfer by establishing a start condition, defined by a high - to - low transition on sda while scl remains high. this indicates that an address/data stream follows. all devices on the bus respond to the start condition and acquire the next eight bits from the master (the 7 - bit address plus the r/ w bit) msb first. the master sends the 7 - bit dev ice address with the r/ w bit to all the slaves on the bus. the device with the matching address responds by pulling the data line (sda) low during the ninth clock pulse. this ninth bit is known as an acknowledge bit. all other device s withdraw from the bus at this point and return to the idle condition. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the first byte means that the master is to write information to the slave, whereas a lo gic 1 means that the master is to read information from the slave after writing the address and repeating the start address. a data transfer takes place until a master initiates a stop condition. a stop condition occurs when sda transitions from low to hig h while scl is held high. stop and start conditions can be detect ed at any stage during the data transfer. if these conditions are asserted out of sequence during normal read and write operations, the ADAU1979 immediately jumps to the idle condition. figure 33 and figure 34 use the following abbreviations: ack = acknowledge no ack = no acknowledge figure 33 . i 2 c write to ADAU1979 single byte figure 34 . i 2 c read from ADAU1979 single byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 addr1 addr0 1 0 0 0 1 start stop scl sda first byte (device address) second byte (register address) third byte (data) r/w 11408-035 ack ADAU1979 ack ADAU1979 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 addr1 addr0 1 0 0 0 1 scl sda third byte (device address) data byte from ADAU1979 r/w 11408-036 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 addr1 addr0 1 0 0 0 1 start scl sda first byte (device address) second byte (register address) r/w no ack stop ack ADAU1979 ack ADAU1979 ack ADAU1979 repeat start
data sheet ADAU1979 rev. 0 | page 23 of 44 i 2 c read and write operations figure 35 shows the format of a single - word i 2 c write operation. every ninth clock pulse, the ADAU1979 issues an acknowledge by pulling sda low. figure 36 shows the format of a burst mode i 2 c write sequence. this figure shows an example of a write to sequential single - byte registers. the ADAU1979 increments its address register after every byte because the requested address corresponds to a register or memory area with a 1 - byte word length. figure 37 shows the format of a single - word i 2 c read operation. note that the first r/ w bit is 0, indicating a write operation. this is because the address still needs to be written to set up the internal address. after the ADAU1979 acknowledges the receipt of the address, the master must issue a repeated start command followed by the chip address byte with the r/ w bit set to 1 (read). this causes the ADAU1979 sda to reverse and begin driving data back to the master. the master then responds every ninth pulse with an acknowledge pulse to the ADAU1979 . figure 38 shows the format of a burst mode i 2 c read sequence. this figure shows an example of a read from sequential single - byte registers. the ADAU1979 increments its address registers after every byte because the ADAU1979 uses an 8 - bit register address. figure 35 to figure 38 use the following abbreviations: s = start bit p = stop bit am = acknowledge by master as = acknowledge by slave figure 35 . single - word i 2 c write format figure 36 . burst mode i 2 c write format figure 37 . single - word i 2 c read format figure 38 . burst mode i 2 c read format s chip address, r/w = 0 as data byte as p register address 8 bits 1 1408-037 s chip address, r/w = 0 as as as register address 8 bits data byte 1 data byte 2 data byte 3 data byte 4 as as as p ... chip address, r/w = 0 1 1408-038 data byte 1 s chip address, r/w = 0 as as p register address 8 bits chip address, r/w = 1 as s 1 1408-039 data byte 1 s chip address, r/w = 0 am register address 8 bits s as as as data byte 2 am ... p chip address, r/w = 1 1 1408-040
ADAU1979 data sheet rev. 0 | page 24 of 44 spi mode by default, the ADAU1979 is in i 2 c mode. to invoke spi control mode, pull clatch low three times. this is achieved by perform - i ng th ree dummy writes to the spi port (the ADAU1979 does not acknowledge these three writes , s ee figure 39 ). beginning with the fourth spi write, data can be written to or read from the device. the ADAU1979 can be taken out of spi mode only by a full reset initiated by power cycling the devi ce. the spi port uses a 4 - wire interface, consisting of the clatch , cclk, cin, and cout signals, and it is always a slave port. the clatch signal go es low at the beginning of a transaction and high at the end of a tran saction. the cclk signal latches c out on a low - to - high transition. cout data is shifted out of the ADAU1979 on the falling edge of cclk and is clocked into a receiving device, such as a microcontroller, on the cclk rising edge. the cin signal carries the serial input data, and the cout signal carries the serial output data. the cout signal remains tristated until a read operation is requested. this allows direct connection to other spi - compatible peripheral cout ports for sharing the same system controller port. all spi transaction s have the same basic generic control word format , as shown in table 15 . a timing diagram is shown in figure 3 . wr ite a ll data msb first. chip address r/ w the lsb of the first byte of an spi transaction is a r/ w bit. this bit determines whether the communication is a read (logic level 1) or a write (logic level 0). this format is shown in table 13. table 13 . spi address and r/ w byte format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 0 0 r/ w register address the 8 - bit address word is decoded to a location in one of the registers. this address is the location of the appropriate register. data bytes the number of data bytes varies according to the register being accessed. during a burst mode sp i write, an initial register address is written followed by a continuous sequence of data for consecutive register locations. a sample timing diagram for a single - word spi write operation to a register is shown in figure 40 . a sample timing diagram of a single - word spi read operation is shown in figure 41 . the cout pin trans itions being high - z to being driven at the beginning of byte 3. in this example, byte 0 to byte 1 contain the device address, the r/ w bit, and the register address to be read. subsequent bytes carry the data from the device. standalo ne mode the ADAU1979 can also operate in standalone mode. howeve r, in standalone mode, the boost converter, microphone bias, and diagnostics blocks are powered down. to set the device in standalone mode, pull the sa_mode pin to iovdd. in this mode, some pins change functionality to provide more flexibility (see table 14 for more information). table 14 . pin functionality in standalone mode pin function 1 setting description addr0 0 i 2 s sai format 1 tdm modes, determined by the sdataout2 pin addr1 0 master mode sai 1 slave mode sai sda 0 mclk = 256 f s , pll on 1 mclk = 384 f s , pll on scl 0 48 khz sample rate 1 96 khz sample rate sdataout2 0 tdm4 lrclk pulse 1 tdm8 lrclk pulse 1 pin functionality, not full pin names, is listed. see table 12 for additional information. table 15 . generic cont rol word format byte 0 byte 1 byte 2 byte 3 1 device address[6:0], r/ w register address[7:0] data[7:0] data[7:0] 1 continues to end of data .
data sheet ADAU1979 rev. 0 | page 25 of 44 figure 39 . spi mode initial sequence figure 40 . spi write to ADAU1979 clocking (sin gle - word write mode) figure 41 . spi read from ADAU1979 clocking (single - word read mode) figure 42 . spi write to ADAU1979 (multiple bytes) figure 43 . spi read from ADAU1979 (multiple bytes) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 clatch cclk cin 1 1408-041 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 clatch cclk cin register address byte device address (7 bits) r/w data byte 1 1408-042 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 clatch cclk cin cout register address byte device address (7 bits) r/w data byte data byte from ADAU1979 1 1408-043 register address byte data byte1 data byte2 device address byte data byte n ? 1 data byte n clatch cclk cin 1 1408-044 device address byte register address byte data byte2 data byte3 data byte1 data byte n ? 1 data byte n clatch cclk cin cout 1 1408-045
ADAU1979 data sheet rev. 0 | page 26 of 44 register summary table 16 . regmap_ ADAU1979 register summary reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 m_po wer [7:0] s_rst reserved pwup 0x00 rw 0x01 pll_control [7:0] pll_lock pll_mute reserved clk_s reserved mcs 0x41 rw 0x02 reserved [7:0] reserved reserved reserved 0x03 reserved [7:0] reserved reserved reserved 0x04 block_power_sai [7:0] lr_pol bclkedge ldo_en vref_en adc_en4 adc_en3 adc_en2 adc_en1 0x3f rw 0x05 sai_ctrl0 [7:0] sdata_fmt sai fs 0x02 rw 0x06 sai_ctrl1 [7:0] sdata_sel slot_width data_width lr_mode sai_msb bclkrate sai_ms 0x00 rw 0x07 sai_cmap12 [7:0] cmap_c2 cmap_c1 0x10 rw 0x08 sai_cmap34 [7:0] cmap_c4 cmap_c3 0x32 rw 0x09 sai_overtemp [7:0] sai_drv_c4 sai_drv_c3 sai_drv_c2 sai_drv_c1 drv_hiz reserved reserved ot 0xf0 rw 0x0a postadc_gain1 [7:0] padc_gain1 0x a 0 rw 0x0b postadc_gain2 [7:0] padc_gain2 0x a 0 rw 0x0c postadc_gain3 [7:0] padc_gain3 0x a 0 rw 0x0d postadc_gain4 [7:0] padc_gain4 0x a 0 rw 0x0e misc_control [7:0] sum_mode reserved mmute reserved dc_cal 0x0 2 rw 0x0f reserved [7:0] reserved reserved reserved reserved 0xff rw 0x10 reserved [7:0] reserved reserved reserved reserved reserved 0x0f rw 0x11 reserved [7:0] reserved reserved reserved reserved reserved reserved reserved reserved 0x00 rw 0x12 reserved [7:0] reserved reserved reserved reserved reserved reserved reserved reserved 0x00 rw 0x13 reserved [7:0] reserved reserved reserved reserved reserved reserved reserved reserved 0x00 rw 0x14 reserved [7:0] reserved reserved reserved reserved reserved reserved reserved reserved 0x00 rw 0x15 reserved [7:0] reserved reserved reserved reserved reserved reserved reserved reserved 0x20 rw 0x16 reserved [7:0] reserved reserved reserved reserved reserved reserved reserved reserved 0x00 rw 0x17 reserved [7:0] reserved reserved reserved reserved reserved reserved 0x18 reserved [7:0] reserved reserved reserved reserved reserved reserved reserved reserved 0x19 asdc_clip [7:0] reserved adc_clip4 adc_clip3 adc_clip2 adc_clip1 0x00 rw 0x1a dc_hpf_cal [7:0] dc_sub_c4 dc_sub_c3 dc_sub_c2 dc_sub_c1 dc_hpf_c4 dc_hpf_c3 dc_hpf_c2 dc_hpf_c1 0x00 rw
data sheet ADAU1979 rev. 0 | page 27 of 44 register details master power and sof t reset register address: 0x00, reset: 0x00, name: m_power the power management control register enable s the boost regulator, microphone bias, pll, band gap reference, adc, and ldo regulator. table 17 . bit descriptions for m_power bits bit name settings description reset access 7 s_rst software reset. the software reset resets all internal circuitry and all control registers to their respective default state s . it is not necessary to reset the ADAU1979 during a power - up or power - down cycle. 0x0 rw 0 normal operation . 1 software reset . [6:1] reserved reserved. 0x00 rw 0 pwup master power - up control. the master power - up control fully powers up or powers down the ADAU1979 . this must be set to 1 to power up the ADAU1979 . individual blocks can be powered down via their respective power control registers. 0x0 rw 0 full power - down . 1 master power -up .
ADAU1979 data sheet pll control register address: 0x01, reset: 0x41, name: pll_control table 18 . bit descriptions for pll_control bits bit name settings description reset access 7 pll_lock pll lock status. pll lock status bit. when set to 1, the pll is locked. 0x0 r 0 pll not locked . 1 pll locked . 6 pll_mute pll unlock automute. when set to 1, it mutes the adc output if pll becomes unlocked. 0x1 rw 0 no automatic mute on pll unlock . 1 automatic mute with pll unlock . 5 reserved reserved. 0x0 rw 4 clk_s pll clock source select. selecting input clock source for pll. 0x0 rw 0 mclk used for pll input . 1 lrclk used for pll input; only supported for sample rates in the range of 32 khz to 192 khz . 3 reserved reserved. 0x0 rw [2:0] mcs master clock select. mcs bits determine the frequency multiplication ratio of the pll. it must be set based on the input mclk frequency and sample rate. 0x1 rw 001 256 f s mclk for 32 khz up to 48 khz (see the pll and clock section for other sample rates). 010 384 f s mclk for 32 khz up to 48 khz (see the pll and clock section for other sample rates). 011 512 f s mclk for 32 khz up to 48 khz ( see the pll and clock section for other sample rates). 100 768 f s mclk for 32 khz up to 48 khz ( see the pll and clock section for other sample rates). 000 128 f s mclk for 32 khz up to 48 khz (see the pll and clock section for other sample rates). 101 reserved . 110 reserved . 111 reserved . rev. 0 | page 28 of 44
data sheet ADAU1979 block power control and serial port cont rol register address: 0x04, reset: 0x3f, name: block_power_sai table 19 . bit descriptions for block_power_sai bits bit name settings description reset access 7 lr_pol sets lrclk polarity 0x0 rw 0 lrclk low then high 1 lrclk high then low 6 bclkedge sets the bit clock edge on which data changes 0x0 rw 0 data changes on falling edge 1 data changes on rising edge 5 ldo_en ldo regulator enable 0x1 rw 0 ldo powered down 1 ldo enabled 4 vref_en voltage reference enable 0x1 rw 0 voltage reference powered down 1 voltage reference enabled 3 adc_en4 adc channel 4 enable 0x1 rw 0 adc channel powered down 1 adc channel enabled 2 adc_en3 adc channel 3 enable 0x1 rw 0 adc channel powered down 1 adc channel enabled 1 adc_en2 adc channel 2 enable 0x1 rw 0 adc channel powered down 1 adc channel enabled 0 adc_en1 adc channel 1 enable 0x1 rw 0 adc channel powered down 1 adc channel enabled rev. 0 | page 29 of 44
ADAU1979 data sheet rev. 0 | page 30 of 44 serial port control register 1 address: 0x05, reset: 0x02, name: sai_ctrl0 table 20 . bit descriptions for sai_ctrl0 bits bit name settings description reset access [7:6] sdata_fmt serial data format 0x0 rw 00 i 2 s data delayed from edge of lrclk by 1 bclk 01 left justified 10 right justified, 24 - bit data 11 right justified, 16 - bit data [5:3] sai serial port mode 0x0 rw 000 stereo (i 2 s, lj, rj) 001 tdm2 010 tdm4 011 tdm8 100 tdm16 [2:0] fs sampling rate 0x2 rw 000 8 khz to 12 khz 001 16 khz to 24 khz 010 32 khz to 48 khz 011 64 khz to 96 khz 100 128 khz to 192 khz
data sheet ADAU1979 rev. 0 | page 31 of 44 serial port control register 2 address: 0x06, reset: 0x00, name: sai_ctrl1 table 21 . bit descriptions for sai_ctrl1 bits bit name settings description reset access 7 sdata_sel sdataoutx pin selection in tdm4 or greater modes 0x0 rw 0 sdataout1 used for output 1 sdataout2 used for output [6:5] slot_width number of bclks per slot in tdm mode 0x0 rw 00 32 bclks per tdm slot 01 24 bclks per tdm slot 10 16 bclks per tdm slot 11 reserved 4 data_width output data bit width 0x0 rw 0 24- bit data 1 16- bit data 3 lr_mode sets lrclk mode 0x0 rw 0 50% duty cycle clock 1 pulse lrclk is a single bclk cycle wide pulse 2 sai_msb sets data to be input/output e ither msb or lsb first 0x0 rw 0 msb first data 1 lsb first data 1 bclkrate sets the number of bit clock cycles per data channel generated when in master mode 0x0 rw 0 32 bclks/channel 1 16 bclks/channel 0 sai_ms sets the serial port into master or slave mode 0x0 rw 0 lrclk/bclk s lave 1 lrclk/bclk m aster
ADAU1979 data sheet rev. 0 | page 32 of 44 channel 1 and channel 2 mapping for output s erial ports register address: 0x07, reset: 0x10, name: sai_cmap12 table 22 . bit descriptions for sai_cmap12 bits bit name settings description reset access [7:4] cmap_c2 adc channel 2 output mapping . 0x1 rw 0000 slot 1 for channel 0001 slot 2 for channel 0010 slot 3 for channel (on sdataout2 in stereo modes) 0011 slot 4 for channel (on sdataout2 in stereo modes) 0100 slot 5 for channel (tdm8+ only) 0101 slot 6 for channel (tdm8+ only) 0110 slot 7 for channel (tdm8+ only) 0111 slot 8 for channel (tdm8+ only) 1000 slot 9 for channel (tdm16 only) 1001 slot 10 for channel (tdm16 only) 1010 slot 11 for channel (tdm16 only) 1011 slot 12 for channel (tdm16 only) 1100 slot 13 for channel (tdm16 only) 1101 slot 14 for channel (tdm16 only) 1110 slot 15 for channel (tdm16 only) 1111 slot 16 for channel (tdm16 only)
data sheet ADAU1979 rev. 0 | page 33 of 44 bits bit name settings description reset access [3:0] cmap_c1 adc channel 1 output mapping. if cmap is set to a slot that does not exist for a given serial mode, that channel is not driven. for example, if cmap is set to slot 9 and the serial format is i 2 s, that channel is not driven. if more than one channel is set to the same slot, only the lowest channel number is driven; other channels are not driven. 0x0 rw 0000 slot 1 for channel 0001 slot 2 for channel 0010 slot 3 for channel (on sdataout2 in stereo modes) 0011 slot 4 for channel (on sdataout2 in stereo modes) 0100 slot 5 for channel (tdm8+ only) 0101 slot 6 for channel (tdm8+ only) 0110 slot 7 for channel (tdm8+ only) 0111 slot 8 for channel (tdm8+ only) 1000 slot 9 for channel (tdm16 only) 1001 slot 10 for channel (tdm16 only) 1010 slot 11 for channel (tdm16 only) 1011 slot 12 for channel (tdm16 only) 1100 slot 13 for channel (tdm16 only) 1101 slot 14 for channel (tdm16 only) 1110 slot 15 for channel (tdm16 only) 1111 slot 16 for channel (tdm16 only)
ADAU1979 data sheet rev. 0 | page 34 of 44 channel 3 and channel 4 mapping for output s erial ports register address: 0x08, reset: 0x32, name: sai_cmap34 table 23 . bit descriptions for sai_cmap34 bits bit name settings description reset access [7:4] cmap_c4 adc channel 4 output mapping 0x3 rw 0000 slot 1 for channel 0001 slot 2 for channel 0010 slot 3 for channel (on sdataout2 in stereo modes) 0011 slot 4 for channel (on sdataout2 in stereo modes) 0100 slot 5 for channel (tdm8+ only) 0101 slot 6 for channel (tdm8+ only) 0110 slot 7 for channel (tdm8+ only) 0111 slot 8 for channel (tdm8+ only) 1000 slot 9 for channel (tdm16 only) 1001 slot 10 for channel (tdm16 only) 1010 slot 11 for channel (tdm16 only) 1011 slot 12 for channel (tdm16 only) 1100 slot 13 for channel (tdm16 only) 1101 slot 14 for channel (tdm16 only) 1110 slot 15 for channel (tdm16 only) 1111 slot 16 for channel (tdm16 only)
data sheet ADAU1979 rev. 0 | page 35 of 44 bits bit name settings description reset access [3:0] cmap_c3 adc channel 3 output mapping 0x2 rw 0000 slot 1 for channel 0001 slot 2 for channel 0010 slot 3 for channel (on sdataout2 in stereo modes) 0011 slot 4 for channel (on sdataout2 in stereo modes) 0100 slot 5 for channel (tdm8+ only) 0101 slot 6 for channel (tdm8+ only) 0110 slot 7 for channel (tdm8+ only) 0111 slot 8 for channel (tdm8+ only) 1000 slot 9 for channel (tdm16 only) 1001 slot 10 for channel (tdm16 only) 1010 slot 11 for channel (tdm16 only) 1011 slot 12 for channel (tdm16 only) 1100 slot 13 for channel (tdm16 only) 1101 slot 14 for channel (tdm16 only) 1110 slot 15 for channel (tdm16 only) 1111 slot 16 for channel (tdm16 only) serial output drive control and overtemperature prot ection status register address: 0x09, reset: 0xf0, name: sai_overtemp table 24 . bit descriptions for sai_overtemp bits bit name settings description reset access 7 sai_drv_c4 channel 4 serial output drive enable. 0x1 rw 0 channel not driven on serial output port . 1 channel driven on serial output port. slot determined by cmap _c4.
ADAU1979 data sheet rev. 0 | page 36 of 44 bits bit name settings description reset access 6 sai_drv_c3 channel 3 serial output drive enable. 0x1 rw 0 channel not driven on serial output port . 1 channel driven on serial output port. slot determined by cmap _c3. 5 sai_drv_c2 channel 2 serial output drive enable. 0x1 rw 0 channel not driven on serial output port . 1 channel driven on serial output port. slot determined by cmap _c2. 4 sai_drv_c1 channel 1 serial output drive enable. 0x1 rw 0 channel not driven on serial output port . 1 channel driven on serial output port. slot determined by cmap _c1. 3 drv_hiz select whether to tristate unused sai channels or actively drive these data slots . 0x0 rw 0 unused outputs driven low . 1 unused outputs h i gh -z. [2:1] reserved reserved 0x0 r 0 ot over t emperature status 0x0 r 0 normal operation . 1 overtemperature fault . post adc gain channe l 1 control register address: 0x0a, reset: 0x a 0, name: postadc_gain1 table 25 . bit descriptions for postadc_gain1 bits bit name settings description reset access [7:0] padc_gain1 channel 1 post adc gain 0x a 0 rw 00000000 +60 db gain 00000001 +59.625 db gain 00000010 +59.25 db gain ... ... 10011111 +0.375 db gain 10100000 0 db gain 10100001 ? 0.375 db gain ... ... 11111110 ? 35.625 d b gain 11111111 mute
data sheet ADAU1979 rev. 0 | page 37 of 44 post adc gain channe l 2 control register address: 0x0b, reset: 0x a 0, name: postadc_gain2 table 26 . bit descriptions for postadc_gain2 bits bit name settings description reset access [7:0] padc_gain2 channel 2 post adc gain 0x a 0 rw 00000000 +60 db gain 00000001 +59.625 db gain 00000010 +59.25 db gain ... ... 10011111 +0.375 db gain 10100000 0 db gain 10100001 ? 0.375 db gain ... ... 11111110 ? 35.625 d b gain 11111111 mute post adc gain channe l 3 control register address: 0x0c, reset: 0x a 0, name: postadc_gain3 table 27 . bit descriptions for postadc_gain3 bits bit name settings description reset access [7:0] padc_gain3 channel 3 post adc gain 0x a 0 rw 00000000 +60 db gain 00000001 +59.625 db gain 00000010 +59.25 db gain ... ... 10011111 +0.375 db gain 10100000 0 db gain 10100001 ? 0.375 db gain ... ... 11111110 ? 35.625 d b gain 11111111 mute
ADAU1979 data sheet rev. 0 | page 38 of 44 post adc gain channe l 4 control register address: 0x0d, reset: 0x a 0, name: postadc_gain4 table 28 . bit descriptions for postadc_gain4 bits bit name settings description reset access [7:0] padc_gain4 channel 4 post adc gain. 0x a 0 rw 00000000 +60 db gain 00000001 +59.625 db gain 00000010 +59.25 db gain ... ... 10011111 +0.375 db gain 10100000 0 db gain 10100001 ? 0.375 db gain ... ... 11111110 ? 35.625 d b gain 11111111 mute high - pass filter and dc o ffset c ontrol register and master mute register address: 0x0e, reset: 0x0 2 , name: misc_control
data sheet ADAU1979 rev. 0 | page 39 of 44 table 29 . bit descriptions for misc_control bits bit name settings description reset access [7:6] sum_mode channel summ ing mode control for higher snr 0x0 rw 00 normal 4 - channel operation 01 2- channel sum ming operation ( see the adc summing modes section ) 10 1- channel sum ming operation ( see the adc summing modes section ) 11 reserved 5 reserved reserved 0x0 rw 4 mmute master mute 0x0 rw 0 normal operation 1 all channels muted [3:1] reserved reserved 0x0 rw 0 dc_cal dc calibration enable 0x0 rw 0 normal operation 1 perform dc calibration adc clipping status register address: 0x19, reset: 0x00, name: asdc_clip table 30 . bit descriptions for asdc_clip bits bit name settings description reset access [7:4] reserved reserved 0x0 rw 3 adc_clip4 adc channel 4 clip status 0x0 r 0 normal operation 1 adc channel clipping 2 adc_clip3 adc channel 3 clip status 0x0 r 0 normal operation 1 adc channel clipping 1 adc_clip2 adc channel 2 clip status 0x0 r 0 normal operation 1 adc channel clipping 0 adc_clip1 adc channel 1 clip status 0x0 r 0 normal operation 1 adc channel clipping
ADAU1979 data sheet rev. 0 | page 40 of 44 digital dc high - pass filter and cali bration register address: 0x1a, reset: 0x00, name: dc_hpf_cal table 31 . bit descriptions for dc_hpf_cal bits bit name settings description reset access 7 dc_sub_c4 channel 4 dc subtraction from calibration 0x0 rw 0 no dc subtraction 1 dc value from dc calibration is subtracted 6 dc_sub_c3 channel 3 d c subtraction from calibration 0x0 rw 0 no dc subtraction 1 dc value from dc calibration is subtracted 5 dc_sub_c2 channel 2 dc subtraction from calibration 0x0 rw 0 no dc subtraction 1 dc value from dc calibration is subtracted 4 dc_sub_c1 channel 1 dc subtraction from calibration 0x0 rw 0 no dc subtraction 1 dc value from dc calibration is subtracted 3 dc_hpf_c4 chann el 4 dc high - pass filter enable 0x0 rw 0 hpf off 1 hpf on 2 dc_hpf_c3 channel 3 dc high - pass filter enable 0x0 rw 0 hpf off 1 hpf on 1 dc_hpf_c2 chann el 2 dc high - pass filter enable 0x0 rw 0 hpf off 1 hpf on 0 dc_hpf_c1 chann el 1 dc high - pass filter enable 0x0 rw 0 hpf off 1 hpf on
data sheet ADAU1979 rev. 0 | page 41 of 44 typical application circuit figure 44 . t ypical application circuit, four input s, i 2 c and i 2 s m ode r17 c20 c21 4.87k? 2200pf 39nf pll input option lrclk mclk 1k? 390pf 5600pf notes 1. r9, r10 = typical 2k? for iovdd = 3.3v, 1k? for iovdd = 1.8v. 2. r11 through r14 used for setting the device in i 2 c mode. 3. r16 = typical 47k? for iovdd = 3.3v, 22k? for iovdd = 1.8v. 4. pll loop filter: i 2 c/spi control c18 10f c19 0.1f c20 c21 r17 +3.3v (avdd2) 10f mlcc x7r c12 0.1f +3.3v c13 0.1f c14 0.1f c15 0.1f r9 r10 r11 r12 r16 c7 0.1f c16 10f mlcc x7r avdd1 avdd3 avdd2 dvdd iovdd lrclk bclk sdataout1 to dsp iovdd sdataout2 scl/cclk sda/cout addr1/cin addr0/clatch pd/rst +1.8v or +3.3v agnd1 agnd3 avdd2 programmable gain decimator/hpf dc calibration serial audio port 3.3v to 1.8v regulator agnd2 agnd2 agnd1 agnd2 agnd3 agnd4 agnd5 agnd6 dgnd vref mclkin pll_filt sa_mode r13 r14 micro- controller ADAU1979 bg ref pll line1 ain1 avdd1 avdd3 adc ain1 adc ain2 ain2 line2 ain3 adc ain3 line3 adc ain4 ain4 line4 * for more information about calculating the value for r ext , see the power-on reset sequence section. r ext * 11408-046 refer to the specifications section for the typical differential input voltage
ADAU1979 data sheet rev. 0 | page 42 of 44 outline dimensions figure 45 . 40- lead lead frame chip scale package [lfcsp_wq] 6 mm 6 mm body, very very thin quad (cp - 40 - 14 ) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option adau 1979 wbcpz C 40c to +105c 40- lead lfcsp_wq cp -40-14 adau 1979 wbcpz -rl C 40c to +105c 40- lead lfcsp, 13 tape and reel cp -40-14 eval - adau 1979 z evaluation board 1 z = rohs compliant part. 2 w = qualified for automotive applications. automotive products the ADAU1979 wbcp z models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models; th erefore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific pr oduct ordering information and to obtain the specific automotive reliability reports for these models. 0.50 bsc bot t om view top view pin 1 indic a t or exposed pa d pin 1 indic a t or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 6.10 6.00 sq 5.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.25 min 4.05 3.90 sq 3.75 compliant to jedec standards mo-220- wjjd . 40 1 11 20 21 30 31 10 05-06-20 1 1- a
data sheet ADAU1979 rev. 0 | page 43 of 44 notes
ADAU1979 data sheet rev. 0 | page 44 of 44 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11408 - 0 - 11/13(0)

▲Up To Search▲

Price & Availability of ADAU1979

	To Download ADAU1979 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .